Capacitors are widely used in integrated circuits (ICs) such as dynamic random access memory (DRAM) devices. Over the years, the density of DRAMs on IC circuits has increased many times over, yet demand for even greater density continues. As DRAM devices become increasingly integrated, there is a need for creating capacitors that occupy less area than have previous capacitors and, ultimately, that occupy minimal IC area, subject to various constraints. Chief among these constraints is the need to preserve the capacitance of the devices even as their area is reduced. ICs are predominantly planar and, in discussing area optimization of a capacitor, it is the plane of the IC and, the reduction of area in that plane, that is of primary concern.
Each DRAM cell includes a single transistor and a capacitor. The capacitor can occupy only a fraction of the DRAM cell area because each capacitor in the DRAM cell must be isolated from adjacent capacitors in an array.
Creating higher capacitances in each DRAM cell is beneficial to maintaining the DRAM's characteristics. Several ways exist in which to increase the DRAM's capacitance. The DRAM's dielectric layer could be made from higher dielectric constant materials, a thinner dielectric layer could be used, or the DRAM could have a larger dielectric layer. However, creating a capacitor structure having the largest possible surface area is the best way to increase the DRAM's capacitance.
Achieving optimal capacitor area is complicated by a number of design challenges. For example, commonly used dielectrics may suffer from limitations as to their required thickness. In recent years, development efforts have focused on creating high-permittivity materials for a DRAM capacitor. Current DRAMs contain capacitors using a thin dielectric sandwiched between two electrodes made of doped crystalline or polycrystalline silicon. Various materials have been tested for their suitability as dielectrics, one of them being the thin-film barium strontium titanate (BSTO). Other possible dielectrics include STO and SBT. Even if these materials prove feasible and practicable, the reduction in size resulting from such material improvements would not necessarily address the entirety of the demand for even further reduced capacitor area.
Without somehow reducing the capacitors' area, however DRAMs cannot continue to be reduced in size relative to the plane of the IC. An unmet need therefore exists for an area-efficient capacitor that occupies minimal IC area, while maintaining its capacitance.